In parallel to the evaluation of new more advanced technologies, there is an interest to study in more detail the readout architecture in the MALTA prototype chip implemented in 180 nm, where the pixels send their address to the periphery over an asynchronous parallel bus immediately upon a hit.  This study includes in particular the treatment of the asynchronous address signals in the periphery and will also include some measurements to benchmark the MALTA architecture. Once the results of this study and of an engineering run to be submitted in Q2 2020 are available, it will be possible to evaluate whether to continue further work and submissions in this technology or move to a more advanced one.