Hybrid pixel detectors remain the detector of choice at the heart of the large general purpose LHC detectors and for the future LHCb VELO upgrade. While there has been and continues to be impressive progress with monolithic pixels, hybrid pixels will probably continue to be necessary in environments where ultimate performance is required. One of the limiting factors associated to hybrid pixels is the high cost associated with flip-chip bump bonding of ASIC and sensor together. This cost is primarily driven by the lack of volume in production that precludes the savings associated with industrial scale processing. Unless new processes are developed that will allow to increase the production volume substantially these costs are unlikely to drop substantially in the coming years. 

Alternative approaches are currently used by the image sensor industry. In these processes image sensor wafers are connected to CMOS readout wafers permitting assembly costs at a fraction of those of the flip-chip bump bonding currently used for HEP chips. One of the medium term aims of this part of the work package is to start prototyping using these processes and ultimately to design a hybrid pixel detector.